LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- aggregator
-- like a bau5

ENTITY aggregator IS
   PORT(
	   clk, reset : IN STD_LOGIC;
	   incomingdata : IN STD_LOGIC;
	   data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	   --data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	   outputs_ready : OUT STD_LOGIC;
	   --count_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
	   meta0_out, meta1_out, meta2_out, meta3_out, meta4_out, meta5_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	   Address : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
       );
END aggregator;

ARCHITECTURE aggregator_arch OF aggregator IS

COMPONENT TestFF IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC 
	);
END COMPONENT;

COMPONENT Counter_12_bit IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		cnt_en		: IN STD_LOGIC ;
		updown		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
	);
END COMPONENT;

COMPONENT actualAddressRegister IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		load		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT Counter_6_bit IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		cnt_en		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
END COMPONENT;


SIGNAL Done : STD_LOGIC;
SIGNAL count : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL meta0, meta1, meta2, meta3, meta4, meta5 : STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

-- Accept data and pass it down.
-- This actually causes more problems than it's worth.
--AmIDone: TestFF PORT MAP (reset, (clk AND NOT(Done)), (count(2) AND count(1) AND NOT(count(0))), Done); 

-- Keep track of how much data I've taken in
CounttheThing : Counter_12_bit PORT MAP(reset, clk, (incomingData), '1', count);

-- Take in data

--data_out <= data_in;
--count_out <= count;

Pass0: actualAddressRegister PORT MAP (reset, (clk), data_in, incomingData, '1', meta0);
Address(7 DOWNTO 0) <= meta0;
meta0_out <= meta0;
Pass1: actualAddressRegister PORT MAP (reset, (clk), meta0, incomingData, '1', meta1);
Address(15 DOWNTO 8) <= meta1;
meta1_out <= meta1;
Pass2: actualAddressRegister PORT MAP (reset, (clk), meta1, incomingData, '1', meta2);
Address(23 DOWNTO 16) <= meta2;
meta2_out <= meta2;
Pass3: actualAddressRegister PORT MAP (reset, (clk), meta2, incomingData, '1', meta3);
Address(31 DOWNTO 24) <= meta3;
meta3_out <= meta3;
Pass4: actualAddressRegister PORT MAP (reset, (clk), meta3, incomingData, '1', meta4);
Address(39 DOWNTO 32) <= meta4;
meta4_out <= meta4;
Pass5: actualAddressRegister PORT MAP (reset, (clk), meta4, incomingData, '1', meta5);
Address(47 DOWNTO 40) <= meta5;
meta5_out <= meta5;

outputs_ready <= ((count(2) AND count(1) AND NOT(count(0))) OR (count(3) AND count(2)));

END aggregator_arch;